Products
Our products are currently available in two different formats; an EDIF core and a VHDL simulation core. An EDIF core is an ASCII file that is associated with a Foundation or ISE schematic symbol or VHDL component. The symbol or VHDL component is placed in your schematic or VHDL file, allowing you to use the core in your FPGA designs. VHDL core files are generated from the schematic source. They can be used for functional simulation in Xilinx Foundation and ISE or customised for your ASIC. Actel, Altera and Lattice FPGA cores are also available on request.

We have four different licensing schemes which all include the EDIF core and VHDL simulation core. All our cores are available under the SignOnce licensing scheme, either as a site or project license. For ASICs, a separate license is available for use of the VHDL core in your ASIC design. The SignOnce and ASIC licenses allow an unlimited number of instantiations of the core. We also have a low cost university license, where a limited number of instantiations can be ordered.

For a quote on any of our cores please send an email to info@sworld.com.au.

PCD03D DVB-RCS and IEEE 802.16e 8 state turbo and 64 state Viterbi decoder.
PCD03V 3GPPTM (UMTS/LTE) and 3GPP2 (cdma 2000 1xEV-DV/1xEV-DO) 8 state turbo and multi state Viterbi decoder.
PCD03VH LTE and 1xEV-DO turbo decoder with ping-pong input and output memories.
PCE03V 3GPPTM (UMTS/LTE) and 3GPP2 (cdma 2000 1xEV-DV/1xEV-DO) 8 state turbo encoder.
PCD04I Inmarsat 16 state turbo and 64/256 state Viterbi decoder.
PCD04C CCSDS 16 state turbo and 64/256 state Viterbi decoder.
PCE04C CCSDS 16 state turbo encoder.
VA08V Multi state Viterbi decoder.
VA08S 64/256 state block Viterbi decoder.
MAP03T Very high speed 8 state MAP decoder.
MAP04T Very high speed 16 state MAP decoder.
MAP04B 16 state MAP decoder.
TINSAT Cansat system with sensors, controller and transmitter
TUFC Timing Unit and Firing Circuit

Last update 31 Mar 2010. Home