The VA08VA is a low complexity 16, 32, 64 or 256 state error control decoder
using the maximum likelihood Viterbi algorithm. The decoder is designed for
maximum flexibility, allowing it to decode various communications standards, as
well as custom coding solutions. The VA08VA is an improved version of the VA08V
offering 8-bit input quantisation, longer and more flexible traceback lengths
and options for decoding terminated or tail-biting convolutional codes.
- 16, 32, 64 or 256 states (memory m = 4, 5, 6 or 8, constraint lengths 5,
6, 7 or 9) Viterbi decoder
- Up to 330 MHz internal clock
- Up to 33 Mbit/s for 16, 32, or 64 states or 9.7 Mbit/s with 256 states
- Rate 1/2, 1/3, 1/4 or 1/5 (inputs can be punctured for higher rates)
- Optional or standard 3GPP/3GPP2 code polynomials
- 8–bit signed magnitude or two's complement input data
- Optional continuous, terminated (1 to 1024-m data bits) or tail-biting
(m to 511 data bits) decoding where m is encoder memory
- Estimated channel bit error outputs
- Optional serial (continuous only) or parallel data input
- Optional automatic symbol synchronisation for rate 1/2 QPSK and rate 1/2
to 1/5 BPSK
- Xilinx 7-Series: Up to 2018 LUTs. 1 to 5 18Kb BlockRAMs. Altera Cyclone
IV: Up to 2104 LEs, 9 to 17 M9K.
- Asynchronous logic free design
- Free simulation software
- Available as EDIF core and VHDL
simulation core for Xilinx FPGAs under SignOnce IP License. Actel, Altera
and Lattice FPGA cores available on request.
- Available as VHDL core for ASICs
- Data Sheet 14 Mar 2017 (v1.04)
Specifications subject to change without notice.
Last update 14 Mar 2017. Home