This is a high speed 16 state CCSDS compatible parallel concatenated turbo
- 16 state CCSDS compatible turbo encoder
- Rate 1/2 to 1/7
- Interleaver sizes from 1784 to 16056 bits
- Up to 250 MHz internal clock
- Up to 125 Mbit/s encoding speed
- Serial continuous encoded data out
- Available as EDIF core and VHDL
simulation core for Xilinx Virtex-II, Spartan-3, Virtex-4, Virtex-5,
Virtex-6 and Spartan-6 FPGAs under SignOnce IP License. Actel, Altera and
Lattice FPGA cores available on request.
- Available as VHDL core for ASICs
- Low cost university license also available
- Data Sheet 4 October 2010 (v1.02)
Specifications subject to change without notice.
Last update 4 Oct 2009. Home