This is a high speed 16 state CCSDS compatible parallel concatenated turbo
- 16 state CCSDS compatible turbo encoder
- Rate 1/2 to 1/7
- Interleaver sizes from 1784 to 16056 bits
- Up to 447 MHz internal clock
- Up to 223 Mbit/s encoding speed
- Serial continuous encoded data out
- 128 LUTs for Virtex-5, Virtex-6 and 7-Series
- Available as VHDL core for Xilinx
FPGAs under SignOnce IP License. ASIC, Actel, Altera, Lattice and
Microsemi cores available on request.
- Data Sheet 7 December 2017 (v1.03)
Specifications subject to change without notice.
Last update 7 Dec 2017. Home