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PCD04C |
PCD04C
This is a CCSDS compatible 16 state error control turbo decoder. The PCD04C
offers unparalleled speed, performance, low complexity and features compared to
other available decoder cores.
Turbo Decoder
- 16 state CCSDS compatible
- Rate 1/2 to 1/7
- Interleaver sizes from 1784 to 16056 bits
- Up to 342 MHz internal clock (log-MAP)
- Up to 33.3 Mbit/s with 5 decoder iterations
- 6-bit signed magnitude input data
- Log-MAP or max-log-MAP constituent decoder algorithms
- Up to 128 iterations in 1/2 iteration steps
- Power efficient early stopping
- Extrinsic information output with optional scaling and limiting
- Full estimated channel error output
- Free
simulation software
Viterbi Decoder (Optional)
- 64 or 256 state (constraint length 7 or 9)
- Rate 1/2, 1/3 or 1/4
- Block lengths from 1784 to 16056 bits
- Up to 9.9 Mbit/s (256 state) or 33.7 Mbit/s (64 state)
- 6-bit signed magnitude input data
- Estimated channel error output
Available as VHDL core for AMD-Xilinx
FPGAs under SignOnce IP License. ASIC, Intel/Altera, Lattice and Microsemi
cores available on request.
- Data Sheet 8 August 2022 (v1.60)
Specifications subject to change without notice.
Last update 26 Aug 2021. Home