The VA08V is a low complexity 16, 32, 64 or 256 state error control decoder
using the maximum likelihood Viterbi algorithm. The decoder is designed for
maximum flexibility, allowing it to decode various communications standards, as
well as custom coding solutions.
- 16, 32, 64 or 256 states (constraint lengths 5, 6, 7 or 9) Viterbi
- Up to 284 MHz internal clock
- Up to 28.4 Mbit/s for 16, 32, or 64 states or 8.3 Mbit/s with 256 states
- Rate 1/2, 1/3, or 1/4 (inputs can be punctured for higher rates)
- Optional or standard code polynomials
- 6–bit received signed magnitude data
- Optional block decoding with or without tail
- Estimated channel bit error outputs
- Optional serial or parallel data input
- Optional automatic synchronisation for rate 1/2 QPSK and rate 1/2 to 1/4
- 856 slices for Virtex-II, Spartan-3 and Virtex-4. 1111 LUTs for
Virtex-5, Virtex-6 and Spartan-6. 1 or 2 BlockRAMs.
- Asynchronous logic free design
- Free simulation software
- Available as EDIF core and VHDL
simulation core for Xilinx Virtex-II, Spartan-3, Virtex-4, Virtex-5,
Virtex-6 and Spartan-6 FPGAs under SignOnce IP License. Actel, Altera
and Lattice FPGA cores available on request.
- Available as VHDL core for ASICs
- Low cost university license also available
- Data Sheet 10 Aug 2011 (v1.30)
Specifications subject to change without notice.
Last update 10 Aug 2011. Home