 |
|
LCD01G |
The LCD01G is a high speed decoder for the GEO Mobile Radio (GMR-1) low density parity check (LDPC) code standard.
Features
- GEO Mobile Radio (GMR-1) compatible
- Nominal code rates of 1/2, 2/3, 3/4, 4/5 and 9/10
- Data lengths from 488 to 8880 bits
- Optional QPSK, 16APSK and 32APSK demapping, descrambling and
deinterleaving
- Includes ping-pong input and output memories
- Up to 500 MHz internal clock
- Up to 300 Mbit/s with 30 decoder iterations
- 8-bit log-likelihood-ratio (LLR) or 9-bit inphase and quadrature two's
complement input data
- Programmable signal points
- Up to 256 iterations
- Scaled min-sum modified Gauss-Seidel decoding algorithm
- Optional power efficient early stopping
- Parity check output
- Xilinx 7-Series: 17,832 LUTs, 49 18KB BlockRAMs. Altera Stratix-II
17,853 ALUTs, 168 M4K; Cyclone IV: 30,930 LEs, 120 M9K; Cyclone V:
17,435 ALUTs, 121 M10K.
-
Available as EDIF and VHDL core for
Xilinx FPGAs under SignOnce IP License. Custom ASIC, Intel/Altera,
Lattice, and Microchip/Microsemi/Actel cores available on request.
- Free
simulation software
- Data Sheet 31 Oct. 2022 (v1.04)
Specifications subject to change without notice.
Last update 1 Nov 2022. Home