PCD03T

This is a TETRA-TEDS compatible 8 state error control turbo decoder. The PCD03T offers unparalleled speed, performance, low complexity and features compared to other available decoder cores.

Turbo Decoder

• 8 state TETRA-TEDS compatible
• Rate 1/2 to 1/3
• 2 to 6144 bit interleaver
• Up to 145 MHz internal clock
• Up to 13.8 Mbit/s with 5 decoder iterations
• 6-bit signed magnitude input data
• Log-MAP or max-log-MAP constituent decoder algorithms
• Up to 32 iterations in 1/2 iteration steps
• Optional power efficient early stopping
• Optional extrinsic information scaling and limiting
• Estimated channel error output
• Free simulation software

• 16 state (constraint length 5)
• Rate 1/4
• Data lengths from 2 to 8188 bits
• Up to 11.5 Mbit/s
• 6-bit signed magnitude input data
• Estimated channel error output

• Available as EDIF core and VHDL simulation core for Xilinx Virtex-II, Spartan-3, Virtex-4, Virtex-5, Virtex-6 and Spartan-6 FPGAs under SignOnce IP License. Actel, Altera and Lattice FPGA cores available on request.
• Available as VHDL core for ASICs
• Low cost university license also available
• Data Sheet 7 March 2011 (v1.01)

Last update 7 Mar 2011. Home