VA06C

The VA06C is a fully parallel 64 state error control decoder using the maximum likelihood Viterbi algorithm for the 4x8PSK (4D 8PSK) multi-dimensional trellis code specified in the CCSDS and ECSS standards.

Features

• 64 state 4x8PSK CCSDS and ECSS compatible Viterbi decoder
• Bandwidth efficiencies of 2, 2.25, 2.5 or 2.75 bit/sym
• Up to 293 MHz 4x8PSK symbol rate
• Up to 3.2 Gbit/s data rate
• Global clock enable
• 6-bit received I and Q data
• Optional differential decoder for phase ambiguity resolution
• Optional automatic 4x8PSK symbol synchronisation
• Estimated symbol error output
• Minimum traceback depth of 33 or 65
• 12,500 6-input LUTs
• Asynchronous logic free design
• Available as EDIF and VHDL core for Xilinx FPGAs under SignOnce IP License. ASIC, Intel/Altera, Lattice and Microsemi/Actel cores available on request.
• Data Sheet 4 July 2023 (v1.02)

Last update 4 Jul 2023. Home