This is a high speed DVB-RCS2 16 state duobinary turbo decoder with four parallel MAP decoders.
- 16 state DVB-RCS2 compatible turbo decoder
- Rate 1/2 or 1/3
- 40 to 4800 bit interleaver
- Up to 192 MHz internal clock
- Up to 136 Mbit/s with 5 decoder iterations
- 6-bit signed magnitude input data
- 4 parallel MAP decoders
- Optional log-MAP or max-log-MAP constituent decoder algorithms
- Up to 32 iterations in 1/2 iteration steps
- Optional power efficient early stopping
- Optional extrinsic information scaling and limiting
- Estimated channel error output
- Available as EDIF core and VHDL
simulation core for Xilinx Virtex-II, Spartan-3, Virtex-4, Virtex-5,
Virtex-6, Spartan 6 and 7-Series FPGAs under SignOnce IP License. Actel,
Altera and Lattice FPGA cores available on request.
- Available as VHDL core for ASICs
- Data Sheet 30 May 2015 (v1.04)
Specifications subject to change without notice.
Last update 30 May 2015. Home