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PCD04I |
This is an Inmarsat compatible 16 state error control turbo decoder. The PCD04I
offers unparalleled speed, performance, low complexity and features compared to
other available decoder cores.
Turbo Decoder
- 16 state Inmarsat compatible
- Rate 1/2, 1/3, 1/4 or 1/5
- Data lengths from 1 to 4092, 6140, 12284 or 22524 bits
- External interleaver address table
- Up to 342 MHz internal clock
- Up to 32.4 Mbit/s with 5 decoder iterations (log-MAP)
- 6-bit signed magnitude input data
- Log-MAP or max-log-MAP constituent decoder algorithms
- Up to 128 iterations in 1/2 iteration steps
- Power efficient early stopping
- Extrinsic information output with optional scaling and limiting
- Estimated channel error output
- Free
simulation software
Viterbi Decoder (Optional)
- 64 or 256 state (constraint length 7 or 9)
- Rate 1/2, 1/3 or 1/4
- Block length from 1 to 32760 (256 state) or 32762 (64 state) bits
- Up to 7.9 Mbit/s (256 state) or 27.0 Mbit/s (64 state)
- 6-bit signed magnitude input data
- Estimated channel error output
Available as EDIF and VHDL core for
Xilinx FPGAs under SignOnce IP License. Custom ASIC, Intel/Altera, Lattice
and Microsemi/Actel cores available on request.
- Data Sheet 8 Nov. 2022 (v1.41)
Specifications subject to change without notice.
Last update 8 Nov 2022. Home