PCD03VH

This is a fully compatible 3GPP^TM LTE and 3GPP2 1xEV-DO Release B turbo decoder with ping-pong input and output memories. The PCD03V offers unparalleled performance, low complexity and features compared to other available 3GPP^TM or 3GPP2 decoder cores.

Turbo Decoder

• 8 state 3GPP^TM LTE and 3GPP2 1xEV-DO Release B compatible
• Rate 1/2, 1/3, 1/4 or 1/5
• 40 to 6144 (3GPP^TM LTE) or 17 to 20730 (3GPP2) bit interleaver
• Includes ping-pong input and output memories
• Optional external interleaver parameters for 3GPP^TM LTE and programmable row coefficients for 3GPP2 interleaver
• Up to 107 MHz internal clock
• Up to 10.2 Mbit/s with 5 decoder iterations
• 6-bit signed magnitude or two's complement input data
• Optional log-MAP or max-log-MAP constituent decoder algorithms
• Up to 128 iterations in 1/2 iteration steps
• Optional power efficient early stopping
• Optional extrinsic information scaling and limiting
• 16 or 24 bit CRC check
• Implement one or two different standards from the one core
• Free simulation software

• Available as EDIF core and VHDL simulation core for Xilinx Virtex-II Pro, Spartan-3, Virtex-4 and Virtex-5 FPGAs under SignOnce IP License. Actel and Lattice FPGA cores available on request.
• Available as VHDL core for ASICs
• Low cost university license also available
• Data Sheet 7 Nov 2012 (v1.05)

Last update 7 Nov 2012. Home