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LCD03C |
LCD03C
The LCD03C is a low complexity decoder for the CCSDS rate 1/2 telecommand (TC) and telemetry (TM) low density parity check (LDPC) standard. The TC decoder implements data lengths of 64 or 256. The optional TM decoder implements a data length of 1024.
Features
- CCSDS TC and TM compatible
- Rate 1/2
- Data lengths of TC 64 and 256 or optional TM 1024 bits
- Includes ping-pong input and output memories
- Up to 624 MHz internal clock
- Up to 2.7 Mbit/s with 30 decoder iterations
- 6-bit two's complement input data
- Up to 256 iterations
- Scaled min-sum decoding algorithm
- Optional power efficient early stopping
- Parity check output
- From 305 to 385 LUTs and 4 to 8 18KB BlockRAMs for Xilinx FPGAs
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Available as EDIF and VHDL core for
Xilinx FPGAs under SignOnce IP License. Custom ASIC, Intel/Altera,
Lattice and Microsemi/Microchip/Actel FPGA cores available on request.
- Free
simulation software
- Data Sheet 1 Mar. 2024 (v1.02)
Specifications subject to change without notice.
Last update 1 Mar 2024. Home