This is a very high speed and fully compatible 3GPPTM LTE turbo decoder with one, two, four or eight parallel MAP decoders.
- 8 state 3GPPTM LTE compatible turbo decoder
- Rate 1/3
- 40 to 6144 bit interleaver
- Up to 280 MHz internal clock
- Up to 204 Mbit/s with 5 decoder iterations
- 6-bit signed magnitude input data
- 1, 2, 4 or 8 parallel MAP decoders
- Optional log-MAP or max-log-MAP constituent decoder algorithms
- Up to 32 iterations in 1/2 iteration steps
- Optional power efficient early stopping
- Optional extrinsic information scaling and limiting
- Estimated channel error output
- Available as VHDL core for Xilinx
FPGAs under SignOnce IP License. Actel, Altera and Lattice FPGA cores
available on request.
- Available as VHDL core for ASICs
- Data Sheet 7 Oct 2016 (v1.13)
Specifications subject to change without notice.
Last update 7 Oct 2016. Home