PCE03V

This is a high speed 8 state 3GPP^TM (UMTS and LTE) and 3GPP2 (1xEV-DV Release D and 1xEV-DO Release B) compatible parallel concatenated turbo encoder.

Features

• 8 state 3GPP^TM (UMTS and LTE) and 3GPP2 (1xEV-DV Release D and 1xEV-DO Release B) compatible turbo encoder
• Rate 1/2, 1/3, 1/4 or 1/5
• 40 to 5114 (3GPP^TM UMTS), 40 to 6144 (3GPP^TM LTE) or 17 to 32768 (3GPP2) bit interleaver
• Implement one, two or four different standards from the one core
• Up to 311 MHz internal clock
• Up to 155 Mbit/s encoding speed
• Serial continuous encoded data out
• Available as VHDL core for Xilinx FPGAs under SignOnce IP License. ASIC, Altera, Lattice and Microsemi cores available on request.
• Data Sheet 30 Nov 2017 (v1.47)

Last update 30 Nov 2017. Home