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LCD01C |
LCD01C
The LCD01C is a very fast decoder for the CCSDS (8160,7136) low density parity check (LDPC) standard.
Features
- CCSDS compatible
- Rate 223/255 (8160,7136)
- Includes ping-pong input and output memories
- Up to 225 MHz internal clock
- Up to 1.6 Gbit/s with 10 decoder iterations
- 6-bit sign-magnitude input data
- Up to 64 iterations
- Scaled min-sum decoding algorithm
- Optional power efficient early stopping
- Parity check output
- Xilinx LUTs: 30.4K Virtex-4, 29.1K Virtex-5, 29.4K Virtex-6 and 7-Series,
166 18KB BlockRAMs. Altera ALUTs 26.9K, 166 M9Ks
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Available as EDIF core and VHDL
simulation core for Xilinx Virtex-II, Spartan-3, Virtex-4, Virtex-5,
Virtex-6, Spartan-6 and 7-Series FPGAs under SignOnce IP License. Actel,
Altera and Lattice FPGA cores available on request.
- Available as VHDL core for ASICs
- Free
simulation software
- Data Sheet 4 Apr 2015 (v1.07)
Specifications subject to change without notice.
Last update 6 Apr 2015. Home