 |
|
VA08VB |
The VA08VB is a medium complexity 16, 32, 64 or 256 state error control decoder
using the maximum likelihood Viterbi algorithm. The decoder is designed for
maximum flexibility, allowing it to decode various communications standards, as
well as custom coding solutions. The VA08VB is a faster version of the VA08VA
with 16 parallel add-compare-select (ACS) circuits that are used in series.
Features
- 16, 32, 64 or 256 states (memory m = 4, 5, 6 or 8, constraint lengths 5,
6, 7 or 9) Viterbi decoder
- Up to 574 MHz internal clock
- Up to 95 Mbit/s for 16, 32, or 64 states or 31 Mbit/s with 256 states
- Rate 1/2, 1/3, 1/4 or 1/5 (inputs can be punctured for higher rates)
- Optional or standard 3GPP/3GPP2 code polynomials
- Signed magnitude or two's complement input data
- Optional 6-bit input with 8 or 10 bit state metrics or 8-bit input with
10 or 12 bit state metrics
- Optional continuous, continuous terminated, block terminated or block
tail-biting decoding
- 1 to 1024-m or 32768-m data bits for terminated or m to 511 data bits for
tail biting
- Estimated channel bit error outputs
- Optional serial (continuous only) or parallel data input
- Optional automatic symbol synchronisation for rate 1/2 QPSK and rate 1/2
to 1/5 BPSK
- From 958 to 2204 LUTs and 1 to 5 18Kb BlockRAMs
- Asynchronous logic free design
- Free simulation software
-
Available as EDIF and VHDL core for
Xilinx FPGAs under SignOnce IP License. ASIC, Intel/Altera, Lattice and
Microsemi/Actel FPGA cores available on request.
- Data Sheet 24 Oct 2023 (v1.01)
Specifications subject to change without notice.
Last update 24 Oct 2023. Home