 |
|
SCD02C |
SCD02C
This is a very high speed 4 state CCSDS compatible serial concatenated
convolutional code (SCCC) turbo decoder with optional QPSK to 64APSK demapper.
Features
- Code rates from 0.355 to 0.899
- Data lengths from 5758 to 43678 bits
- Interleaver sizes from 8640 to 65520 bits
- Optional QPSK, 8PSK, 16APSK, 32APSK and 64APSK demapping and deinterleaving with 10-bit inphase and quadrature two's complement input
- Optional demapped 8-bit sign magnitude log-likelihood-ratio (LLR) input
- Includes ping-pong input and output memories
- Optional log-MAP or max-log-MAP constituent decoder algorithms
- 60 parallel MAP decoders (1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 20, 24, 30, 40 or 120 parallel MAP decoders on request)
- Up to 356 MHz internal clock
- Up to 787 Mbit/s (146 Msym/s) with 10 decoder iterations
- Up to 64 iterations
- Programmable signal points option
- Optional power efficient early stopping
- Optional extrinsic information scaling and limiting
- Estimated channel error output
- Free simulation software
Available as EDIF and VHDL core for
Xilinx FPGAs under SignOnce IP License. ASIC, Intel/Altera, Lattice and
Microsemi/Actel cores available on request.
- Data Sheet 12 Oct. 2026 (v1.00)
Specifications subject to change without notice.
Last update 12 Oct. 2026. Home