PCD04CH

This is a CCSDS compatible 16 state error control turbo decoder with optional synchronisation, optional descrambling and input memory. The PCD04CH offers unparalleled speed, performance, low complexity and features compared to other available decoder cores.

Features

• 16 state CCSDS compatible
• Rate 1/2, 1/3, 1/4 or 1/6
• Interleaver sizes from 1784 to 16056 bits
• Includes optional automatic synchronisation to non-inverted or inverted sync marker, optional descrambler and ping-pong input memory
• Up to 343 MHz internal clock (log-MAP)
• Up to 33.3 Mbit/s with 5 decoder iterations
• 6-bit signed magnitude input data
• Log-MAP or max-log-MAP constituent decoder algorithms
• Up to 32 iterations in 1/2 iteration steps
• Power efficient early stopping
• Optional scaling and limiting of extrinsic information
• Full estimated channel error output
• Free simulation software

• Available as VHDL core for AMD-Xilinx FPGAs under SignOnce IP License. ASIC, Intel/Altera, Lattice and Microsemi/Actel cores available on request.
• Data Sheet 28 Dec. 2023 (v1.08)

Last update 28 Dec. 2023. Home