MAP04B

This is a high speed 16 state maximum a posteriori (MAP) soft-in-soft-out (SISO) error control decoder with log-likelihood-ratio outputs for both the data and parity bits.

Features

• 4, 8, or 16 state soft-in-soft-out (SISO) maximum a posteriori (MAP) error control decoder and systematic recursive convolutional encoder
• Up to 2.5 Mbit/s decoding speed for all states
• Rate 1/2, 1/3, or 1/4 with optional punctured inputs
• Optional microprocessor interface
• 6-bit received data, 8-bit soft-in and soft-out data for information and parity bits for all rates
• 8-bit branch metric inputs for rate 1/2
• Continuous or block decoding (with or without tail)
• Programmable code polynomials
• Able to decode (n,n-4) cyclic block codes
• Minimum decoding depth (MDD) of 32 or 64
• Low decoding delay (from 66 to 257 bits).
• 17 programmable SNR's for optimum performance
• No external RAM required
• Asynchronous logic free design (except for global reset, no set or reset signals are used)
• Ideal for iterative decoding of parallel or serial concatenated turbo codes
• Available as BIT/MCS files for download into Xilinx XC4000 or Spartan field programmable gate arrays (FPGA) or EDIF core
• Data Sheet

Last update 24 Nov 2000. Home