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LCD01C |
LCD01C
The LCD01C is a very fast decoder for the CCSDS (8160,7136) low density parity check (LDPC) standard.
Features
- CCSDS compatible
- Rate 223/255 (8160,7136)
- Includes ping-pong input and output memories
- Up to 488 MHz internal clock
- Up to 3.5 Gbit/s with 10 decoder iterations
- 6-bit sign-magnitude input data
- Up to 64 iterations
- Scaled min-sum decoding algorithm
- Optional power efficient early stopping
- Parity check output
- 23,453 6-input LUTs, 166 18KB BlockRAMs. 26,800 Altera ALUTs, 166 M9Ks.
- Asynchronous logic free design
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Available as EDIF and VHDL core for
Xilinx FPGAs under SignOnce IP License. ASIC, Intel/Altera, Lattice and
Microsemi/Actel cores available on request.
- Free
simulation software
- Data Sheet 14 Aug 2023 (v1.08)
Specifications subject to change without notice.
Last update 14 Aug 2023. Home